1. Familiar with hardware design specifications and RTL code development.
2. Familiar with optimization of area area, performance and power consumption for 16nm clips and below.
3. Familiar with chip development process .
4. Familiar with the hardware implementation and optimization of the algorithm.
5. Familiar with the overall process and implementation of the project.
1. Master's degree in computer, electronics, communication, microelectronics, etc., with knowledge of digital electric circuit design,computer architecture and so on.
2. Proficiency in code development with Verilog / VHDL language; familiar with the development environment of Xilinx/Altera FPGA.
3. Familiar with the use of mainstream development tools such as DC/PT/ICC.
4. Understand the use of mainstream scripting languages such as TCL/PERL/Python.